1. Field of the invention.
The invention relates to the field of error testing semiconductor memories and logic circuits. More specifically, to the field of testing any cross coupled latches such as static RAM memories and inverters in periphery circuits.
2. Prior Art.
Error testing of semiconductor memories to determine the exact failed cell is well known in the art. For example, a conventional method such as a logic analyzer can be used to generate a map of failed cells. Based on the cell map, failure analysis tools such as liquid crystal analysis or an emission microscope are used to locate the faulty cell and give additional information as to the cause of failure. For example, a liquid crystal analysis could reveal a leaky hot spot on n-channel or p-channel transistors or an emission microscope could reveal oxide leakage.
Electrical signature analysis methods have been developed in which voltages are applied to failed cells to measure the transistor parameters in order to determine the cause of the failure. Furthermore, the technique is capable of identifying the source of the transistor failure by distinguishing various transistor leakage currents. However, there has always been the problem that previous signature analysis techniques could not test the individual transistor parameters without physical isolation. Physical isolation consists of cutting the lines connecting the transistor to the rest of the IC, thus destroying its utility. So it was impossible to use previous signature analysis techniques on integrated circuits without destroying their utility.
With CMOS static RAM technology, the individual transistors are densely packed, so physical separation is nearly impossible on such high-density chips without damage. Other techniques can be used to find some causes of transistor failure, but none are as thorough or reliable as the present invention. For example, liquid crystal techniques can find leaky transistors but it can not establish the exact location or parameters to determine exactly where the leakage occurs. Laser or photoresist isolation methods can measure parameters but they have proved to be time consuming and difficult, and these techniques can damage the device so that the results are often inconclusive.
Measuring individual transistor parameters is crucial to device design and process testing. Current methods for doing so are unreliable, difficult, and usually destroy the device tested. Also, because of the etch rate of a plasma etcher being different for high and low circuit density regions, a technique for measuring individual transistor parameters in different circuit density areas would provide valuable information for process control and design verification. Until now, there was no such measurement technique available.